E3 - Common COTS Interfaces

Electronics and Eco-design

UKSA Space Cluster Microcredentials

03

Module 3-Common COTS Interfaces

1. Universal Asynchronous Rx/Tx (UART).Gain an appreciation of the ubiqutous UART standard.2. Inter Integrated Circuit (I2C).Investigate the interface requirements for I2C.3. Serial Peripheral Interface (SPI).Form an understanding of the functionality and use case of SPI.4. Implementing Interfaces in SoftwareA light touch investigation into software solutions for interfacing technologies.

learning objectives

With a significant portion of CubeSat hardware delivered through the COTS route it is a requirement for differing hardware from different manufacturers to be easily interfaced to one another. Many standard connection protocols have been developed but there are three that are commonly implemented within systems*:UART (Universal Asynchronous Receive Transmit) I2C (Inter-Integrated Chip) SPI (Serial Peripheral Interface) *One or more of these are often implemented.

CubeSats COTS Interfaces

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This module provides information on the basic operation of each of these interfaces as well as providing example software which could be used for configuration* and operation. *Software examples implemented on Microchip PIC18F devices.

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Asynchronous Communication - UART is asynchronous, meaning that there is no separate clock signal shared between the devices. Instead, both the transmitting and receiving devices agree on a common baud rate, which defines the speed of communication. Data Frame - Data is sent in chunks known as frames. A typical UART frame consists of start and stop bits, along with a set number of data bits (usually 8 bits). The start bit indicates the beginning of the data, and the stop bit(s) mark the end. Baud Rate - The baud rate is the speed at which data is transmitted, and both communicating devices must be configured to use the same baud rate. Common baud rates include 9600, 19200, 38400, and higher, depending on the application requirements.

UART

UART is a communications protocol used for parallel to serial data transfer between devices. It provides a simple and widely adopted method for two devices to exchange data. UART has the following key aspects:

CubeSats COTS Interfaces - UART

Start and Stop Bits - Each UART frame begins with a start bit, followed by the actual data bits, and ends with one or more stop bits. The start bit helps the receiver identify the beginning of the frame, while the stop bit(s) indicate its end. Data Flow - UART communication involves two pins: one for transmitting (TX) and one for receiving (RX). The TX pin of one device is connected to the RX pin of the other, creating a point-to-point communication link. Configurability - UART communication parameters, such as data frame format, parity, and stop bits, can often be configured to suit the specific needs of a given application. This flexibility makes UART a versatile choice for various communication scenarios.

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UART is a communications protocol used for parallel to serial data transfer between devices. It provides a simple and widely adopted method for two devices to exchange data. UART has the following key aspects:

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UART interfaces have standard bit rates (typically 9600bps – 115kbps) although hardware rate is often programmable. Data rate is often automatically detected. Find out more here:

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The UART data format consists of a 8-bit (commonly) or 9-bit Word. Discover UART word format here:

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An example of the UART interface from the Microchip PIC 18F series of devices is given here. This particular interface supports the following features:

• Full-duplex asynchronous transmit and receive
• Two-character input buffer
• One-character output buffer
• Programmable 8-bit or 9-bit character length
• Address detection in 9-bit mode
• Input buffer overrun error detection
• Received character framing error detection
• Programmable clock and data polarity

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The PIC 18F series has a standard two-pin interface (Tx/Rx) and small number of configuration registers for hardware setup… The EUSART device is configured using 4 registers to control the transmission and reception of serial data.

• Transmit Status and Control (TXSTA)
• Receive Status and Control (RXSTA)
• Baud Rate Control (BAUDCON)
• PORT Pin Control (PORTC)

The following code snippets demonstrate set-up at code level.

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Master-Slave Architecture - In an I2C system, there is typically one master device and one or more slave devices. The master initiates communication and controls the data transfer. Addressing - Each slave device on the I2C bus has a unique address, allowing the master to select and communicate with specific slaves. Two-Wire Communication - The SDA line carries the actual data, while the SCL line provides the clock signal for synchronization.

I2C

I2C, or Inter-Integrated Circuit, is a widely used synchronous serial communication protocol. It's designed to allow multiple devices to communicate with each other using just two wires: a data line (SDA) and a clock line (SCL).I2C has the following key aspects:

CubeSats COTS Interfaces - i2c

Bi-directional Communication - Both the master and slave devices can send and receive data on the same bus. Serial Communication - Data is sent bit by bit, starting with the most significant bit (MSB). Pull-up Resistors - Pull-up resistors are often used to keep the data and clock lines high when not actively transmitting.

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I2C, or Inter-Integrated Circuit, is a widely used synchronous serial communication protocol. It's designed to allow multiple devices to communicate with each other using just two wires: a data line (SDA) and a clock line (SCL).I2C has the following key aspects:

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An example of the I2C interface from the Microchip PIC 18F series of devices follows. This particular interface supports either I2C or SPI. In I2C configuration the hardware supports the following:

• All master and slave functions (including general call support).
• Interrupts on Start and Stop bits to determine a free bus (multi-master function).
• Standard mode specifications as well as 7-bit and 10-bit addressing.

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The PIC 18F series has the standard two-pin interface (SCL/SDA) and six configuration registers for I2C hardware setup to control the transmission and reception of serial data.

• MSSP Control Register 1 (SSPCON1)
• MSSP Control Register 2 (SSPCON2)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer Register (SSPBUF)
• MSSP Shift Register (SSPSR)
• MSSP Address Register (SSPADD)

The following code snippets demonstrate set-up at code level.

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The PIC 18F hardware provides control through direct polling or interrupt. Interrupt based monitoring can allow for reduced processor overhead as events are only required to be handled when they occur. The following code snippet describes a typical Interrupt Service Routine (ISR) implementation which allows for a dedicated number of Tx/Rx ‘Words’ or an extended Tx only implementation.

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Investigation 1

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Investigation 2

Use the following websites and/or your own resources to investigate I2C Operation. Once complete look through the PIC 18F I2C code snippets. You should be able to identify some key features of operation.

Investigate i2c Interfaces

Synchronous Communication - SPI is a synchronous protocol, meaning that data is transferred in sync with a clock signal. This allows for high-speed communication between devices. Master-Slave Architecture - In an SPI communication setup, there is one master device and one or more slave devices. The master controls the communication and initiates data transfer to or from the slaves. Multiple Slave Devices - SPI supports communication with multiple slave devices using separate chip select lines. The master selects a particular slave device by activating its corresponding chip select (CS) line.Full-Duplex Communication - SPI allows simultaneous communication in both directions (full-duplex). This means that data can be sent from the master to the slave and from the slave to the master at the same time.

spi

Serial Peripheral Interface (SPI) is a synchronous serial communication protocol used for communication between microcontrollers, sensors, displays, memory devices, and other peripheral devices. It allows multiple peripheral devices to be connected to a single microcontroller or microprocessor, and it's commonly used in embedded systems. SPI has the following key aspects:

CubeSats COTS Interfaces - spi

A Four Wire Interface - SPI typically uses four lines for communication:

• MOSI (Master Out Slave In) - The master sends data to the slave on this line.
• MISO (Master In Slave Out) - The slave sends data to the master on this line.
• SCLK (Serial Clock) - The clock signal generated by the master to synchronize data transfer.
• SS/CS (Slave Select/Chip Select) - A separate line for each slave device, used by the master to select the target slave for communication.

Shift Register Operation - Data is shifted out of the master's and into the slave's shift registers simultaneously. The clock edge determines when the data is sampled. Configurable Data Rates - SPI typically supports a wide range of clock frequencies, allowing users to select the appropriate speed for their application.

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SPI is widely used in various applications due to its simplicity, versatility, and high-speed capabilities. It's important to note that while SPI is a common communication protocol, there are variations in its implementation between different microcontrollers and manufacturers. It's essential to consult the specific documentation for the microcontroller or peripheral device you are working with to ensure proper configuration. Click the icon below for further details on SPI's key aspects:

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As described when discussing I2C, the Microchip PIC 18F Master Synchronous Serial Port (MSSP) module supports either I2C or SPI (link to I2C section).The SPI configuration allows eight bits of data to be synchronously transmitted and received simultaneously.The following code snippets discuss PIC 18F pin configuration and demonstrate set-up at code level.

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Investigation 3

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Investigation 4

Use the following websites and/or your own resources to investigate SPI Operation. Once complete look through the PIC 18F I2C code snippets. You should be able to identify some key features of operation.

Investigate SPI Interfaces

Network Data Buffering – due to the nature of some network types (e.g, Ethernet, WiFi, Internet) some traffic may arrive out-of-order, with large delays or require retransmission. Equally a small, networked embedded device may struggle to deal with I/O tasks and manipulating network data at peak traffic times. It this therefore necessary to buffer network data so that data can be processed run all expected data has been received or when core processing power is made available. Video/Audio Buffering – this is often used mitigate interrupted play back of the digital media. In order to ensure that the media can be streamed to the user without interruption the system will store a certain amount of the media data before initiating playback. This data storage is known as buffering. Once data has been buffered, this can be used to offer a ‘stall free’ service to the user even if the remaining data stream is slow or ‘bursty’.

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In order to handle intermittent data being passed over these interfaces it is necessary to be able to receive/transmit data when the host CPU may be operating on other tasks. One solution is to implement Buffer Descriptors and Buffer Rings via interrupt. Buffers are simply a dedicated area of memory used to store data. Buffers appear in many differing applications but are commonly used for the same thing – to store data before it is used. Click the icon below to see common reasons that a system may wish to employ this technique:

CubeSats COTS Interfaces - software

Data Buffer Rings - Data buffer rings are common place in ‘C’ network drivers. A data buffer ring works on the premise that the designer (or function user) implements a data buffer for storing all incoming network data. This is commonly implemented using a technique known as Buffer Descriptors. Buffer Descriptors are a relatively small memory sections (usually < 10 bytes) which are used to point to a section of the receive Data Buffer. The buffer descriptors usually provide information on the data located at the prescribed buffer area, how many bytes should be received before interrupting the ‘upper layer’ software and where/when the data buffer should ‘wrap’ back to the start. Usually there are several buffer descriptors assigned to a data buffer.Buffer Descriptors have the key advantage of allowing the upper layer to set how many bytes should be received before notification – so that the differing sizes of data packet can be acted upon, as well as providing an ‘automatic’ feature for wrapping back to the start of the data buffer.

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In order to handle intermittent data being passed over these interfaces it is necessary to be able to receive/transmit data when the host CPU may be operating on other tasks. One solution is to implement Buffer Descriptors and Buffer Rings via interrupt. Buffers are simply a dedicated area of memory used to store data. Buffers appear in many differing applications but are commonly used for the same thing – to store data before it is used. Click the icon below to see common reasons that a system may wish to employ this technique:

CubeSats COTS Interfaces - software... continued

The following example implements a buffer descriptor ring… Here the Buffer Descriptors (Top) contain how many bytes have been received to the data buffer followed by how many are left to receive before interrupting management software. Note that the data buffer (Bottom) contains the actual data received from the network for each Buffer Descriptor. The final Buffer Descriptor has received only 2 bytes with 8 bytes still remaining before issuing interrupt. This buffer descriptor will also wrap back to the beginning of the buffer ring.

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Upper Layer (Management) Software configures how the buffer descriptors should initiated. Notice that these buffer descriptors are set to WIFI_BUFFER_SIZE. Data is received into the data buffer with the buffer descriptor ring updated accordingly.

The interrupt service routine is initially implemented to handle low level data reception according to Buffer Descriptor layout.

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In order to detect the falling edge of the start bit the UART hardware usually runs from a clock running at 16 times the bit rate. Having seen the falling edge of the start bit the UART waits for one and a half bit times before checking the line for the remaining bits of data. This should ensure that the last bit of the word is still identified correctly even if there is a slight difference in clock speeds. If the receiver detects a logic 0 when it is expecting a stop bit, this will be flagged as a framing error.

As the PIC 18F MSSP shares I2C and SPI hardware it provides direct polling or interrupt control as seen with I2C. The following code snippet describes a typical Interrupt Service Routine (ISR) implementation which allows for a dedicated number of Transmission ‘Words’. Note that SPI’s operation as a full duplex communications protocol allows us to use Transmission Buffer Descriptors (TmBD) rather than dedicated Tx/Rx BD’s

UART data format:

• A start bit, always logic 0
• Seven or eight data bits, least significant bit first
• An optional parity bit
• One or two stop bits

PIC 18F devcices support all four modes of SPI. To accomplish communication, typically three pins are used:

• Serial Data Out – SDO
• Serial Data In – SDI
• Serial Clock – SCK

Additionally, a fourth pin may be used when in a Slave mode of operation:

• Slave Select – SS

The associated PIC 18F MSSI pins can be seen here along with code snippets demonstrate set-up at code level.