Venus7 Initial

Venus7 Preliminary

Xinji Corporation Confidential and Proprietary

Overview

• PDK Characterization
• Device Optimization
• Device Selection
• Efficiency Verification

• Control Loop
• Layout
• Roadmap
• Timeline

Xinji Corporation Confidential and Proprietary

PDK Characterization

• Layout device pitch checked so device width could be translated to physical area
• A single 1mm2 chunk of FET was simulated for rdson, Qg and Qrr
• Voltage coefficients and temperature coefficients were also extracted for more accurate calculations
• Extracted parameters put into a config file for calculations

Xinji Corporation Confidential and Proprietary

Device Optimization

• The device parameters were collected and the optimization performed for 3.8Vin, 1.2Vout, 4MHz switching, and 1A
• The efficiency calculations were updated, correcting some errors as well as converting to script format rather than spreadsheet. This makes it possible to change conditions rapidly
• The efficiency is now calculated in an iterated loop to first estimate power dissipation and calculate the resulting temperature change
• Each point on the plot to the right is the result of roughly 100 conditions checked - device size swept at each device size constraint, and the best point picked and efficiency plotted
• With the Venus1 sizing, circled in red, we are very far from optimal
• If I could squeeze in 50% more die area and get to 0.1mm2, that could make a HUGE difference and get us over 84%

Xinji Corporation Confidential and Proprietary

Device Selection

• Efficiency sweeps show 3.8Vin and 1.2Vout
• cstar18 devices shown for reference
• Significantly better efficiency using pldmos_5v (81.2%) vs pldmos_6v (78.2%)
• Virtually no difference between nldmos with and without isolation

Xinji Corporation Confidential and Proprietary

Device Selection

• The process layers used are dictated by the PLDMOS, which only has an NBL option for some reason.
• The DNW layer will also be used to be able to contact NBL as well as for the vertical NPN

Xinji Corporation Confidential and Proprietary

Constrained Efficiency

• Using the same device area as Venus1, plotting for different Vout (1.0V, 1.2V, 3.0V)
• The peak efficiencies aren't awful, but the 1A optimization point is far beyond the peaks
• Can see in the loss breakdown that the conduction loss by far dominates all other losses

1A, 89%

1A, 81%

1A, 78%

Xinji Corporation Confidential and Proprietary

Simulation Verification

• By implementing a simple control loop with the selected device sizes, the calculations can be verified
• What's listed as "Conduction Loss" includes all FET losses other than gate charge. This is because it's difficult to separate conduction, QRR and Transition loss in simulation
• I am in the process of reconciling a scaling issue that is making the simulated LS rdson appear more than 20% off from the predicted value

This discrepancy could account for as much as 3% total efficiency

Xinji Corporation Confidential and Proprietary

Control Loop

• The simulated control loop is showing much better load regulation than I would have expected based on the calculations in the lower right
• This may be because the current ripple is small enough that the loop is straddling voltage mode and current mode operations, but I need to investigate further before concluding the load regulation will be fine
• Don't mind the jitter, it appears to be a simulation precision artifact

Xinji Corporation Confidential and Proprietary

Layout

• Let's see where there's room for area savings
• How big is the new OTP IP?
• If I can cut down on the number of trimmed parameters we could reduce some of the digital area.
• Could I get stats on the ATE trim history so we can see if there are some bits that just never get used?
• Need to clarify some specs
• I see FB control has been requested, but the ripple injection method used by Venus1 relies on having both FB and VOUT - we produce the FB internally from VOUT
• We could change the control scheme but that will cost some time and maybe complexity

• The customer specifies a minimum frequency of 3MHz, but also requests high efficiency down to 1mA, which is a bit of a conflict
• If the customer really only wants one operating mode, we could consider dropping the MODE pin and replacing with VOUT sense
• We can do all the area saving we can and finalize power device area at the end

Xinji Corporation Confidential and Proprietary

Roadmap

• Finalize device selection and layers
• In addition to the power devices we'll need the 3k hi-R poly, mim caps, and 3 metal layer option
• We also need to get the package layers into the PDK - RDL, RV and UBM. Who is the packaging house?
• Port existing IP into new PDK
• SKILL code acquired, need to make mapping files
• Need example of the OTP IP
• Evaluation request to applications team

• Trim Venus1 to max ILIM (111 on bits 24:26). This should get 1.9A max
• I need to see if SW node still looks normal or if the gate signals are getting corrupted
• This will determine if we need to add a sub-regulator to analog block and/or level shifters
• Capture SW and PVIN ringing magnitude on rising and falling edges
• Calculate efficiency at max current
• Design work

• Update control feedback network
• Update current limit for higher current
• Confirm comparator is sufficient for smaller sense ripple
• Test and top level verification sims

Xinji Corporation Confidential and Proprietary

Timeline

• If the PDK conversion tool works, it should be possible to finish by end of May
• Considering there are a lot of unknowns still, realistically finish by end of June

Xinji Corporation Confidential and Proprietary